FPGA/RTL Design Engineer - (Eau Claire, WI)

We have a 6 mnth contract opportunity for a FPGA/RTL Design Engineer in Eau Claire, WI. Position summary/Skills needed: 5yrs of FPGA design background, preferably Xilinx FPGAs. Background with going through 3-5 Iarge FPGAs through complete design cycle, from RTL to timing driven synthesis to place & route, static timing analysis. 5+ years of RTL, - Verilog, System - Verilog, - VHDL background 5+ years of FPGA design background, preferably Xilinx FPGAs Comfortable with Perl and C Ability with Synplify, - VCS, Modelsim and Xilinx ISE tool Background with USB, microprocessor, SDIO/SD/eMMC, Audio at RTL Ievel will be plus Logic analyzer, PCB/hardware bring up and debug will be plus Protocol Ievel RTL implementation knowledge on USB/OTG, PCIe, eMMC, SDIO/SD, ARC or some microcontroller, SPI, DDR2 memory. Expert in computer architecture and some understanding on PCB board Ievel hardware. Diploma or GED equivalent required.