Presi Validation Engineering - (Hudson, MA)

Pre-si Validation Engineering Position details In this position, you will be a validation manager in the pre-silicon IP validation team in Intel's Scalable Performance CPU Development Group (SDG). You will be responsible for validating the CPU coherency fabric design IP for high-end, server-oriented computing products. Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.