Sr. NVM Layout Architect and Pathfinding Engineer Folsom, CA - (Folsom, CA)

Sr. NVM Layout Architect and Pathfinding Engineer Job overview In this position, you will be part of Intel's Centralized Design Acceleration and Operations team CDAO working on Physical Design Mask Design and innovative technology development in support of next generation Non-Volatile Memory. You will be required to assume a technical leadership role in the layout development of 3DNAND and/or 3DXPoint media ICs. You may also contribute key technical solutions for other Intel IC/ASIC design teams focusing on the introduction of Next Generation technologies such as Silicon Photonics SPPD, DCG, Perceptual Computing Intel RealSense - PerC, NTG or Intel Labs. Roles and Responsibilities: Solid Experience 15yrs or more with Non-Volatile Memory Layout Typically performs as a highly proficient technical individual contributor or specialist on complex layout and leadership assignments.