Principal Engineer DDR PHY Architect Lead - (Folsom, CA)

Principal Engineer- DDR PHY Architect Lead Position description Applicant will lead the PHY Architecture development for modular, scalable, high-performance, low-power, next-generation Memory Interfaces on latest Intel process technologies for multiple exciting Intel SoC products. Defines, Documents and Designs PHY Architectures for High-Performance/Low-Power Memory Interfaces supporting multiple Intel SoC applications. Determines creative design approaches and parameters. Determines, specifies and evaluates the viability of complex hardware features and structures and ensures that firmware and hardware designs interface correctly. Designs framework for particular functions. Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or firmware compatibility. Identifies, analyzes and resolves subsystem and/or SoC design weaknesses.