Design Engr - Verification III) - (Chandler, AZ)

Should have 10 years. background in analog mixed-signal design andor simulation. three years simulation specific background desired nbsp MS or PhD Electrical Engineering Degree preferred nbsp Strong communication expertise, both written and verbal nbsp Must be high-energy, proactive and detail-oriented capable of exercising independent judgment nbsp Projects are global in nature, so applicant must have flexibility in hours worked. Ability in following tools nbsp - AMS designer nbsp - Verilog, VerilogA, VerilogAMS, System Verilog, net-types nbsp - Connect rules and modules nbsp - Initial AMS setup, Convergence of simulator for analog and mixed signal simulation with devices and models nbsp - Hierarchy editor and use of editor to enable circuit configurations to accelerate simulation while retaining appropriate accuracy nbsp - OSSUNL netlister Mentor analog and digital designers on simulation techniques and develop tools and methodologies to streamline mixed-signal design for top-level and block-level.